- Ultra-fast fault analysis, reducing months of simulation to days
- Low effort coverage boosting to increase accuracy with low overhead
- Reduced resource, time-to-market and effort with increase ASIL rating
Hard errors, or permanent faults in an automotive device are states that become stuck at 1 or stuck at 0, and may also be bridging faults between two states, tristate faults, and others. These are usually created by a damaged transistor that can easily occur in a hot, vibrating, high-pressure environment, such as a car.
These faults need to be detected within 0.25mS – 100mS of their occurrence, depending on their criticality and the device timing budget. This requires the entire device to be guarded using robust Safety Mechanisms, which are running continuously. In an ASIL-D device, greater than 99% of possible faults needed to be guarded by a Safety Mechanism. Optima-HE™ provides a significantly enhanced and complete solution for Hard Error fault verification and analysis.
Various Safety Mechanisms are leveraged to eliminate the affect of these hard errors. These might include BIST techniques, Lock Step operation for processors, a Software Test Library (STL), Error Correcting Codes, and many others. The Optima-HE Safety-BISTmechanism may be included that provides an enhanced L-BIST solution that operates on-the-fly during device operation.
To ensure that full and complete coverage of all the possible faults in the design, extensive fault simulation must be performed. A simulation with a comprehensive set of test vectors is run on a clean design, and then the same design with a fault injected on every node. Faults are classified based on their ability to propagate to a Safety Mechanism, and then by their elimination by the Safety Mechanism. This simulation must be performed at the gate level on the final device code prior to fabrication.
This fault simulation process, using traditional simulation, often requires months of simulation running on multiple machines, even with extensive fault collapsing and pruning applied. Optima-FIE™ fault simulation technology reduces this to hours of runtime, saving significant time and therefore allowing for higher quality results and greater design coverage to be engineered. The Fault simulation makes use of a range of acceleration techniques and can also be run in parallel on multiple machines
The fault analysis process is only as good as the tests that are applied to the simulation. A high coverage of the design is therefore absolutely critical, and this can be hard to achieve for some of these complex blocks. Optima-HE includes CoverageBooster™, a powerful mechanism that allows for specific, uncovered nodes to be listed. This automated solution enables full coverage of blocks to be achieved easily and quickly.
Optima-HE Fault Analysis Display
Optima-HE is able to produce a full set of results, classifying faults as safe or unsafe, and further decomposing these into detected and residual faults. It also calculates the single point fault metric and provides an overall measure of coverage.